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d a t a sh eet product speci?cation supersedes data of 1995 sep 18 file under integrated circuits, ic17 1996 oct 22 integrated circuits uaa2067g image reject 1800 mhz transceiver for dect applications
1996 oct 22 2 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g features receiver with: C low noise amplifier C dual quadrature mixers for image rejection (lower sideband) C i and q combining networks at a fixed if both high-frequency and low-frequency vcos including buffers with good isolation for low pulling transmitter with: C dual quadrature mixers for image rejection (lower sideband) C amplitude ramping circuit C amplifier with high output power. applications 1800 mhz transceiver for dect hand-portable equipment tdma systems. general description the uaa2067g is a low-power transceiver intended for use in portable and base station transceivers complying with the dect system. the ic performs in accordance with specifications in the - 30 to +85 c temperature range. the uaa2067g contains a front-end receiver for the 1800 to 1900 mhz frequency range, a high-frequency vco for the 1650 to 1850 mhz range, a low-frequency vco for the 100 to 140 mhz frequency range and a transmitter with a high-output power amplifier driver stage for the 1800 to 1900 mhz frequency range. designed in an advanced bicmos process, it combines high performance with low-power consumption and a high degree of integration, thus reducing external component costs and total radio size. its first advantage is to provide typically 34 db of image rejection in the receiver path. thus, the image filter between the lna and the mixer is redundant and consequently can be removed. the receive section consists of a low-noise amplifier that drives a quadrature mixer pair. image rejection is achieved by this rf mixer pair and the two phase shifters in the i and q channels that phase shift the if by 45 and 135 respectively. the two phase shifted ifs are recombined and buffered to furnish the if output signal. signals presented at the rf input at lo - if frequency are rejected through this signal processing while signals at lo + if frequency can form the if signal. its second advantage is to provide a good buffered high-frequency vco signal to the rx and tx mixers and to the synthesizer-prescaler. switching the receive or transmit section on gives a very small change in vco frequency. its third advantage is to provide a good buffered low-frequency vco signal to the tx mixers, to the synthesizer-prescaler and the second down conversion mixer in a double conversion receiver. switching the transmit section on gives a very small change in vco frequency. the frequency of each vco is determined by a resonator network that is external to the ic. each vco has a regulated power supply voltage that has been designed specifically for minimizing a change in frequency due to changes in the power supply voltage, which may be caused for instance by switching on the power amplifier. its fourth advantage is to provide typically 33 dbc of image rejection in the single-sideband up-conversion mixer. thus the image filter between the power amplifier and the antenna is redundant and may consequently be removed. image rejection is achieved in the internal architecture by two rf mixers in quadrature and two phase shifters in the low-frequency vco signal that shifts the phase to 0 and 90 . the output signals of the mixers are summed to form the single-upper-sideband output signal. the output stage is a high-level output buffer with an output power of approximately 4 dbm. the output level is sufficient to drive a three-stage bipolar preamplifier for dect. ordering information type number package name description version uaa2067g lqfp32 plastic low pro?le quad ?at package; 32 leads; body 5 5 1.4 mm sot401-1
1996 oct 22 3 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g quick reference data for conditions see chapters dc characteristics and ac characteristics. symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.6 5.5 v i cc(rx) receive supply current - 24 - ma i cc(tx) transmit supply current - 42 - ma i cc(rflo) rf oscillator supply current - 15 - ma i cc(iflo) if oscillator supply current - 7 - ma nf rx receive noise ?gure -- 7.0 db g cp conversion power gain - 30 - db ir rx receive image frequency rejection - 34 - db f rflo rflo frequency range 1.65 - 1.85 ghz f iflo iflo frequency range 100 - 140 mhz p out output transmit power - 4 - dbm ir tx transmit image frequency rejection - 33 - dbc t amb operating ambient temperature - 30 +25 +85 c
1996 oct 22 4 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g block diagram handbook, full pagewidth 0 o 90 o 45 o 135 o rflo oscillator 0 o 90 o 5 1 6 7 2 4 uaa2067 3 8 14 mgc867 11 10 9 12 13 19 16 17 24 21 20 15 22 23 18 29 28 32 27 31 pdrx gnd6 v cc(mix) v cc1(rflo) v cc2(rflo) v cc(rfloo) gnd4 gnd5 rfloa rflob rfloreg v cc(tx) gnd3 gnd7 rxa rxb txa txb pdtx txramp pdrflo rfloo v cc(iflo) gnd2 gnd1 iflores ifloreg pdiflo ifloo icen ifdec ifo 30 26 25 iflo oscillator lna ramp ? ? fig.1 block diagram.
1996 oct 22 5 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g pinning notes 1. pins 3 and 7 are internally short-circuited. 2. pins 11 and 27 should be at the same dc voltage. 3. pins 18 and 23 are internally short-circuited. 4. pins 19 and 22 are internally short-circuited. symbol pin description pdiflo 1 power-down for iflo ifloreg 2 regulator decoupling for iflo gnd1 3 ground for iflo; note 1 ifloo 4 iflo output v cc(iflo) 5 supply voltage for iflo iflores 6 iflo resonator gnd2 7 ground for iflo resonator; note 1 icen 8 ic enable pdtx 9 power-down for transmitter txramp 10 power ramping transmitter v cc(tx) 11 supply voltage for transmitter output stage; note 2 txb 12 transmitter rf output b txa 13 transmitter rf output a gnd3 14 ground for transmitter output stage pdrflo 15 power-down for rflo v cc(rfloo) 16 supply voltage for rflo output rfloo 17 rflo output v cc1(rflo) 18 supply voltage for rflo oscillator; note 3 gnd4 19 ground for rflo oscillator; note 4 rfloa 20 rflo resonator rflob 21 rflo resonator gnd5 22 ground for rflo oscillator; note 4 v cc2(rflo) 23 supply voltage for rflo oscillator; note 3 rfloreg 24 regulator decoupling for rflo ifo 25 receiver if output ifdec 26 if decoupling v cc(mix) 27 supply voltage for receive and transmit mixers; note 2 rxa 28 receiver rf input a rxb 29 receiver rf input b gnd6 30 ground for receive and transmit mixers pdrx 31 power-down for receiver gnd7 32 die-pad ground
1996 oct 22 6 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g fig.2 pin configuration. handbook, full pagewidth uaa2067 mgc865 1 2 3 4 5 6 7 8 pdiflo ifloreg gnd1 ifloo v cc(iflo) iflores gnd2 icen rfloreg v cc2(rflo) gnd5 rflob rfloa gnd4 v cc1(rflo) rfloo 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 pdtx txramp v cc(tx) txb txa gnd3 pdrflo v cc(rfloo) 32 31 30 29 28 27 26 25 gnd7 pdrx gnd6 rxb rxa v cc(mix) ifdec ifo
1996 oct 22 7 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g functional description receive section the circuit contains a balanced low-noise amplifier followed by two high dynamic range mixers. the local oscillator signals, shifted in phase to 0 and 90 mix the amplified rf signal to the i and q channels.these two channels are buffered, phase shifted by 45 and 135 respectively, amplified and recombined internally to realize the image rejection. signals at the rf input at rflo - if frequencies are rejected through the signal processing while signals at the rflo + if frequencies form the if signals. an image rejection of typically 34 db is obtained for an if between 100 and 120 mhz. balanced signals are used for minimizing crosstalk due to package parasitics. the if output is single-ended. the typical load is 50 w . fast switching, on/off of the receive section is controlled by the hardware input pdrx. rflo section the high-frequency oscillator (rflo oscillator) supplies the local oscillator signal for the down-conversion (receive) and up-conversion (transmit) mixers. this vco uses an on-chip regulator for a power-supply voltage-independent output frequency. the buffered vco signal is fed into a phase shifter and an off-chip prescaler-synthesizer. the output signal of the phase-shifter is used for driving the rx and tx mixers. due to the good isolation in the buffer stages, a very small change in vco frequency is obtained when switching the rx and tx mixers on . fast switching, on/off of the oscillator section is controlled by the hardware input pdrflo. iflo section the low-frequency oscillator (iflo oscillator) internally supplies the local oscillator signal to the single-sideband transmit mixer. the buffered vco signal is fed into a phase shifter. the output signal of the phase-shifter is used for driving the tx mixers. due to the good isolation in the buffer stages, a very small change in vco frequency is obtained when switching the tx mixer on . fast switching on/off of the oscillator section is controlled by the hardware input pdiflo input. transmit section the circuit contains two balanced mixers, each of which is driven by the rflo and iflo signals. the output signal of the two mixers is summed and buffered to obtain the single upper-sideband signal at frequency rflo + iflo. with the use of an off-chip time constant, the ramping circuit defines the power ramp-up and ramp-down of the pre-amplifier output signal. balanced signals are used for minimizing crosstalk due to package parasitics. fast switching, on/off , of the transmit section is controlled by the hardware input pdtx. the power supply voltage of the transmit mixers, the adding circuit and ramping circuit is taken from the v cc(mix) and gnd6 for maximum isolation from the preamplifier output stage. operating modes to use the ic, all v cc pins must be connected to the supply voltage. for transceiving a dect signal, the rflo and iflo sections should be powered-on. after a stable frequency has been reached (mainly determined by the synthesizer design), the receiver or transmitter can be powered-on. gmsk data modulation can be supplied in two different ways: the data is directly modulated on iflo or rflo. the ramping of the power level can be set with a time constant that is external to the ic. table 1 gives the definition of the polarity of the switching signals on the receive, the rflo, the iflo and the transmit sections.
1996 oct 22 8 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g table 1 switching signals on the receiver note 1. active when icen is enabled. limiting values in accordance with the absolute maximum rating system (iec 134). note 1. pins short-circuited internally must be short-circuited externally. thermal characteristics handling every pin withstands the esd test in accordance with mil-std-883c class 2 (method 3015.5) . signal section level on/off pdrx receive section powered-on low on (1) receive section powered-off high off pdrflo rflo section powered-on low on (1) rflo section powered-off high off pdiflo iflo section powered-on low on (1) iflo section powered-off high off pdtx transmit section powered-on low on (1) transmit section powered-off high off icen all sections disabled low off all sections enabled high on symbol parameter conditions min. max. unit v cc supply voltage - 6v d gnd difference in ground supply voltage applied between all grounds note 1 - + 0.3 v p l(max) maximum power input - +20 dbm t j(max) maximum operating junction temperature - +150 c p dis(max) maximum power dissipation in stagnant air at 25 c - 500 mw t stg storage temperature - 65 +150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 90 k/w
1996 oct 22 9 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g dc characteristics v cc = 3.6 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit pins: v cc(mix) , v cc(tx) , v cc(iflo) , v cc1(rflo) , v cc2(rflo) and v cc(rfloo) v cc supply voltage over full temperature range 3.0 3.6 5.5 v i cc(rx) supply current receive section on ; dc tested 18 24 30 ma i cc(rflo) supply current rflo rflo section on ; dc tested 11 15 20 ma i cc(iflo) supply current iflo iflo section on ; dc tested 5 7 9 ma i cc(tx) supply current transmit section on ; dc tested 34 42 54 ma i cc(pd) supply current power-down mode; dc tested - 250 m a pins: pdrx, pdtx, pdrflo, pdiflo and icen v ih high level input voltage 2.1 - v cc + 0.3 v v il low level input voltage - 0.3 - 0.8 v i ih high level static input current pin at v cc - 0.4 v - 1 - +1 m a i il low level static input current pin at 0.4 v - 1 - +1 m a pins: rxa, rxb, ifo and ifdec v rxa,b dc input voltage level receive section on 2.1 2.4 2.7 v v ifo dc output voltage level receive section on 0.9 1.1 1.3 v v ifdec dc level receive section on 2.45 2.65 2.85 v pins: rfloa, rflob, rfloreg and rfloo i rfloa,b dc current rflo section on 123 ma v rfloreg dc level rflo section on 2.45 2.65 2.85 v v rfloo dc output voltage level rflo section on 2.8 3.1 3.4 v pins: iflores, ifloreg and ifloo v iflores dc level iflo section on 1.85 2.1 2.3 v v ifloreg dc level iflo section on 2.35 2.55 2.8 v v ifloo dc output voltage level iflo section on 2.2 2.45 2.7 v pins: txa, txb and txramp i txa,b dc output current transmit section on 21018 ma i txramp dc input current v txramp =3v; transmit section on -- 200 m a
1996 oct 22 10 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g ac characteristics v cc = 3.0 to 5.5 v; t amb = - 30 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit receive mode (receive and rflo sections powered-on) f rfi rf input frequency 1800 - 1900 mhz r irf rf input resistance (real part of the parallel input impedance) balanced; at 1890 mhz - 190 -w c irf rf input capacitance (imaginary part of the parallel input impedance) balanced; at 1890 mhz - 0.8 - pf prflo rx rflo level at input to rx balun note 1 -- 70 - 40 dbm des3 rx rf interference for 3 db desensitization interference frequency offset 6 mhz; note 1 -- 35 - dbm g cp conversion power gain rf input to if output (typical load) over full temperature range 24 30 36 db t amb =25 c273033db cp1 rx 1 db input compression point referenced to rf input; note 1 - 36 - 33 - dbm p o(rx) if power for cp1 rx

1996 oct 22 11 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g rf local oscillator (rflo section powered-on) f rflo(min) minimum oscillator frequency range 1650 - 1850 mhz r i(rflo) oscillator input resistance (real part of the parallel input impedance) balanced; at 1.77 ghz -- 250 -w c i(rflo) oscillator input capacitance (imaginary part of the parallel input impedance) balanced; at 1.77 ghz - 2.7 - pf v o(rflo) local oscillator output level at pin 17; rms value note 2; typical load resistance 50 75 - mv z o(rflo) local oscillator output impedance at pin 17 at 1.77 ghz - 30 - 60j -w r l(rflo) typical load resistance - 300 -w har (rflo) harmonic levels at rflo output (pin 17) note 1 -- - 20 dbc if local oscillator (iflo section powered-on) f iflo(min) minimum oscillator frequency range 100 120 140 mhz r i(iflo) oscillator input resistance (real part of the parallel input impedance) -- 480 -w c i(iflo) oscillator input capacitance (imaginary part of the parallel input impedance) - 2.1 - pf v o(iflo) if local oscillator output level at pin 4; rms value 100 160 - mv z o(iflo) local oscillator output impedance (real part) -- 100 w r l(iflo) typical load resistance - 5 - k w c l(iflo) typical load capacitance - 7 - pf har (iflo) harmonic levels at iflo output note 1 -- - 15 dbc symbol parameter conditions min. typ. max. unit
1996 oct 22 12 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g notes 1. measured and guaranteed only on the philips demonstration board, including pcb and balun. 2. the imaginary part of the load impedance has been tuned out. a power match is assumed. 3. a simplified dect type approval measurement is used; the spectrum analyser has the following settings: rbw = 100 khz, vbw = 100 hz, use delta marker and add 50 db (correction for rbw = 100 khz), f rflo = 1.77 ghz and f iflo = 120 mhz, d f = 4.686 mhz. transmit mode (transmit, rflo and iflo sections powered-on) f tx rf output frequency 1800 - 1900 mhz r o(tx) rf output resistance (real part of the parallel output impedance) balanced; note 1 - 110 -w c o(tx) rf output capacitance (imaginary part of the parallel output impedance) balanced; note 1 - 0.6 - pf ftrflo tx rflo feedthrough at the tx output referenced to the desired frequency; t amb =25 c; note 1 -- 25 - 23 dbc pout output transmit power v txramp = 0 v; note 1 over full temperature range - 2 4 8 dbm t amb =25 c 1 4 7 dbm ir tx image frequency rejection referenced to the desired frequency; note 1 over full temperature range 20 33 - dbc t amb =25 c2333 - dbc z intxramp input impedance at pin txramp 10 -- k w c intxramp input capacitance at pin txramp -- 10 pf v txramp(max) ramp voltage for p out =p max - 0v v txramp(min) ramp voltage for p out =p max - 30 db - 3.0 - v cnr tx carrier-to-noise ratio at tx output t amb =25 c; notes 1 and 3 +130 +133 - dbc/hz timing t up start-up/power-down time of each block over full temperature range - 510 m s c i input capacitance of logic inputs over full temperature range -- 5pf symbol parameter conditions min. typ. max. unit
1996 oct 22 13 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g internal pin configuration symbol pin dc voltage (v) equivalent circuit pdiflo 1 - icen 8 - pdtx 9 - pdrflo 15 - pdrx 31 - ifloreg 2 2.55 rfloreg 24 2.65 ifdec 26 2.65 gnd 3, 7, 14, 19, 22, 30, 32 0 ifloo 4 2.45 v cc 5, 11, 16, 18, 23, 27 3.6 iflores 6 2.1 mbh672 v cc gnd 1, 8, 9, 15, 31 mbh673 v cc gnd 2, 24, 26 mbh674 v cc(iflo) gnd 4 mbh675 v ifloreg gnd 6
1996 oct 22 14 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g txramp 10 - txb 12 v cc txa 13 v cc rfloo 17 3.1 rfloa 20 2.0 rflob 21 2.0 symbol pin dc voltage (v) equivalent circuit mbh676 v cc(mix) v cc(tx) gnd 10 mbh677 12 13 v cc(tx) gnd mbh678 v cc(rfloo) gnd 17 mbh679 20 21 v rfloreg gnd
1996 oct 22 15 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g ifo 25 1.1 rxa 28 2.4 rxb 29 2.4 symbol pin dc voltage (v) equivalent circuit mbh680 v cc(iflo) gnd 25 mbh681 v cc(mix) gnd 28 29
1996 oct 22 16 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g application information handbook, full pagewidth mod tune v cc bb515 bb515 bby 5103w rflo output bby 5103w rflo tune mgc866 v cc r3 4.7 k w r2 10 k w l1 82 nh c8 150 pf c6 10 pf c5 22 nf c9 4.7 pf c14 1 nf c13 10 pf c7 1 nf 5.6 nh 5.6 nh 12 nh 1 pf tx output 1 pf 8.2 pf 8.2 pf v cc 1/4 l txramp r4 4.7 k w 8.2 nf pdtx c11 10 pf icen c10 10 pf l6 (0603) 1.5 nh l7 (0603) 1.5 nh c25 22 pf c26 22 pf c27 10 pf r8 1 k w r7 1 k w 8.2 pf c28 22 nf c32 4.7 nf c31 1 nf c30 1 nf c29 10 pf c1 10 pf c39 10 pf c4 1 nf c2 1 nf c24 4.7 nf c23 8.2 pf c22 10 pf c19 10 pf c20 1 nf c21 10 pf 6.8 nh 6.8 nh 6.8 nh 8.2 pf 8.2 pf rf input iflo output 0.82 pf 0.82 pf 1/4 l 1/4 l r5 33 w r6 33 w v cc v cc v cc pdrflo uaa2067 c33 10 pf c34 1 nf if output pdrx pdiflo 24 26 25 27 28 29 30 31 32 7 8 6 54321 23 22 21 20 19 18 17 15 16 14 13 12 11 10 9 1/4 l fig.3 demonstration board diagram. figure 3 illustrates the electrical diagram of the uaa2067g philips demonstration board for dect applications. all matching is t o 50 w for measurement purposes. different values will be used in a real application.
1996 oct 22 17 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g application-indicative values measured on the philips demonstration board, including pcb and balun at t amb =25 c. note 1. including psrr of the rflo circuitry. symbol parameter conditions min. typ. max. unit rf local oscillator (rflo section powered-on) cnr rflo carrier-to-noise ratio d f = 864 khz - 117 - dbc/hz d f = 2500 khz - 128 - dbc/hz d f = 4686 khz - 134 - dbc/hz pull rflo pulling due to enabling rx or tx v txramp =3v - 5 - khz shift rflo frequency shift due to 200 mv v cc change - 5 - khz if local oscillator (iflo section powered-on) cnr iflo carrier-to-noise ratio d f = 4686 khz - 140 - dbc/hz spur iflo spurious signal modulation due to 0.5 mv (rms value) on the power supply d f = 4686 khz; measured at tx output -- 60 - dbc pull iflo pulling due to enabling tx - 1 - khz shift iflo frequency shift due to 200 mv v cc change - 2.5 - khz transmit mode (transmit, rflo and iflo sections powered-on) psrr tx spurious signal modulation due to 0.5 mv (rms value) on v cc(mix) , v cc(tx) and v cc(rflo) only d f = 4686 khz; note 1 -- 74 - dbc spur tx spurious signals rflo - 3iflo -- 40 - dbc rflo + 2iflo -- 35 - dbc rflo + 5iflo -- 51 - dbc n tx white noise level at the output - 135 - dbc/hz
1996 oct 22 18 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g package outline 0.2 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 0.5 7.15 6.85 1.0 0.95 0.55 7 0 o o 0.12 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot401-1 95-12-19 97-08-04 d (1) (1) (1) 5.1 4.9 h d 7.15 6.85 e z 0.95 0.55 d b p e e b 8 d h b p e h v m b d z d a z e e v m a x 1 32 25 24 17 16 9 q a 1 a l p detail x l (a ) 3 a 2 y w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm sot401-1 c pin 1 index
1996 oct 22 19 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all lqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for lqfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering lqfp packages lqfp32 (sot401-1), lqfp48 (sot313-2), lqfp64 (sot314-2) or lqfp80 (sot315-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 oct 22 20 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 oct 22 21 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g notes
1996 oct 22 22 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g notes
1996 oct 22 23 philips semiconductors product speci?cation image reject 1800 mhz transceiver for dect applications uaa2067g notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 647021/1200/02/pp24 date of release: 1996 oct 22 document order number: 9397 750 01437

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